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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? supports at&t tr62411 and bellcore gr-1244- core stratum 3, stratum 4 enhanced and stratum 4 timing for ds1 interfaces ? supports itu-t g.813 op tion 1 clocks for 2048 kbit/s interfaces ? supports itu-t g.812 type iv clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces ? supports etsi ets 300 011, tbr 4, tbr 12 and tbr 13 timing for e1 interfaces ? selectable 19.44 mhz, 1.544mhz, 2.048mhz or 8khz input reference signals ? provides c1.5, c2, c4 , c6, c8, c16 , and c19 (sts-3/oc3 clock divided by 8) output clock signals ? provides 5 styles of 8 khz framing pulses ? holdover frequency accuracy of 0.05 ppm ? holdover indication ? attenuates wander from 1.9hz ? fast lock mode ? provides time interval error (tie) correction ? accepts reference inputs from two independent sources ? jtag boundary scan applications ? synchronization and timing control for multitrunk t1,e1 and sts-3/oc3 systems ? st-bus clock and frame pulse sources november 2003 ordering information MT9045an 48 pin ssop -40 c to +85 c MT9045 t1/e1/oc3 syst em synchronizer data sheet figure 1 - functional block diagram zarlink semiconductor us patent no. 5,602,884, uk patent no. 0772912, france brevete s.g.d.g. 0772912; germany dbp no. 69502724.7-08 ieee 1149.1a reference select feedback tie corrector enable control state machine state select state select frequency select mux input impairment monitor output interface circuit reference select mux tie corrector circuit ms1 ms2 fs1 fs2 tck sec rst rsel vdd vss tclr c1.5o c19o c2o c4o c8o c16o f0o f8o f16o osco osci master clock tdo pri tdi tms trst c6o rsp tsp holdover flock pcci lock reference monitor prioor secoor virtual reference selected reference dpll
MT9045 data sheet 2 zarlink semiconductor inc. description the MT9045 t1/e1/oc3 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links and sts-3/oc3 links. the MT9045 generates st-bus clock and framing signals th at are phase locked to either a 19.44 mhz, 2.048mhz, 1.544mhz, or 8khz input reference. the MT9045 is compliant with at&t tr62411 and bellco re gr-1244-core stratum 3, stratum 4 enhanced, and stratum 4 and etsi ets 300 011; and itu-t g.813 option 1 fo r 2048 kbit/s interfaces. it will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wande r, frequency accuracy, capture range, phase change slope, holdover frequency and mtie requirements for these specifications. figure 2 - pin connections 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 trst tdi tdo prioor ic fs1 fs2 ic rsel ms1 ms2 vdd ic ic nc vss pcci holdover vdd rst secoor sec pri vdd osco osci vss f16o tsp f8o c1.5o c2o c4o c19o 48 tms v ss 21 27 c6o flock 22 26 vss 23 25 c8o ic 24 c16o tck rsp f0o tclr vdd lock ssop
MT9045 data sheet 3 zarlink semiconductor inc. pin description pin # name description 1,10, 23,31 v ss ground. 0 volts. (vss pads). 2rst reset (input). a logic low at this input resets the MT9045. to ensure proper operation, the device must be reset after reference signal frequency changes and power-up. the rst pin should be held low to a minimum of 300ns. while the rst pin is low, all frame pulses except rst and tsp and all clock outputs except c6o, c16o and c19o are at logic high. the rst, tsp, c6o, c16o are at logic low during reset. the c19o is free-running during reset. following a reset, the input reference so urce and output clo cks and frame pulses are phase aligned as shown in figure 13. 3tclr tie circuit reset (input). a logic low at this input resets the time interval error (tie) correction circuit resulting in a realignment of input phase with output phase as shown in figure 13. the tclr pin should be held low for a minimum of 300ns. this pin is internally pulled down to vss. 4 secoor secondary reference out of capture range (output). a logic high at this pin indicates that the secondary reference is off the nominal frequency by more than 17 ppm. 5 sec secondary refere nce (input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be used. the selection of the input reference is based upon the ms1, ms2, rsel, and pcci control inputs.this pin is internally pulled up to v dd . 6pri primary reference (input). see pin description for sec. this pin is internally pulled up to v dd . 7,17 28,35 v dd positive supply voltage. +3.3v dc nominal. 8osco oscillator master cloc k (cmos output). for crystal operation, a 20mhz crystal is connected from this pin to osci, see figure 9. not suitable for driving other devices. for clock oscillator operation, this pin is left unconnected, see figure 8. 9osci oscillator master clock (cmos input). for crystal operation, a 20mhz crystal is connected from this pin to osco, see figure 9. for clock oscillator operation, this pin is connected to a clock source, see figure 8. 11 f16o frame pulse st-bus 8.192 mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mb/s. see figure 14. 12 f0o frame pulse st-bus 2.048mb/s (cmos output). this is an 8khz 244ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048mb/s and 4.096mb/s. see figure 14. 13 rsp receive sync puls e (cmos output). this is an 8khz 488ns active high framing pulse, which marks the beginning of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 15. 14 tsp transmit sync pulse (cmos output). this is an 8khz 488ns active high framing pulse, which marks the beginning of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 15. 15 f8o frame pulse (cmos output). this is an 8khz 122ns active high framing pulse, which marks the beginning of a frame. see figure 14.
MT9045 data sheet 4 zarlink semiconductor inc. 16 c1.5o clock 1.544mhz (c mos output). this output is used in t1 applications. 18 lock lock indicator (cmos output). this output goes high when the pll is frequency locked to the input reference. 19 c2o clock 2.048mhz (cmos output). this output is used for st-bus operation at 2.048mb/s. 20 c4o clock 4.096mhz (cmos output). this output is used for st-bus operation at 2.048mb/s and 4.096mb/s. 21 c19o clock 19.44mhz (cmos output). this output is used in oc3/sts3 applications. 22 flock fast lock mode (input). set high to allow the pll to quickly lock to the input reference (less than 500 ms locking time). 24 ic internal connection. tie low for normal operation. 25 c8o clock 8.192mhz (c mos output). this output is used for st-bus operation at 8.192mb/s. 26 c16o clock 16.384mhz (cmos output). this output is used for st-bus operation with a 16.384mhz clock. 27 c6o clock 6.312 mhz (cmos output). this output is used for ds2 applications. 29 hold over holdover (cmos output). this output goes to a logic high whenever the pll goes into holdover mode. 30 pcci phase continuity control input (input). the signal at this pin affects the state changes between primary holdover mode and primary normal mode, and primary holdover mode and secondary normal mode. the logic level at this input is gated in by the rising edge of f8o. see table 4. 32 nc no connection. leave open circuit 33,34 ic internal connection. tie low for normal operation. 36 ms2 mode/control select 2 (input). this input determines the state (normal, holdover or freerun) of operation. the logic level at this in put is gated in by the rising edge of f8o. see table 3. 37 ms1 mode/control select 1 (input). the logic level at this input is gated in by the rising edge of f8o. see pin description for ms2. this pin is internally pulled down to vss. 38 rsel reference source select (input). a logic low selects the pri (primary) reference source as the input reference signal and a logic high selects the sec (secondary) input. the logic level at this input is gated in by the rising edge of f8o. see table 2. this pin is internally pulled down to vss. 39 ic internal connection. tie low for normal operation. 40 fs2 frequency select 2 (input). this input, in conjunction with fs1, selects which of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be input to the pri and sec inputs. see table 1. 41 fs1 frequency select 1 (input). see pin description for fs2. 42 ic internal connection. tie low for normal operation. 43 prioor primary reference out of capture range (output). a logic high at this pin indicates that the primary reference is off the nominal frequency by more than 17 ppm. pin description (continued) pin # name description
MT9045 data sheet 5 zarlink semiconductor inc. functional description the MT9045 is a multitrunk system sy nchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for t1 and e1 primary rate digital transmission links. figure 1 is a functional block diagram which is described in the following sections. reference select mux circuit the MT9045 accepts two simultaneous reference input signals and operates on their falling edges. either the primary reference (pri) signal or the secondary refere nce (sec) signal can be selected as input to the tie corrector circuit. the selection is based on the control, mode and reference selection of the device. see table 1 and table 4. frequency select mux circuit the MT9045 operates with one of four possible inpu t reference frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz). the frequency select inputs (fs1 and fs2) dete rmine which of the four frequencies may be used at the reference inputs (pri and sec). both inputs must have the same frequency applied to them. a reset (rst ) must be performed after every frequency select input change. see table 1. table 1 - input frequency selection time interval error (t ie) corrector circuit the tie corrector circuit, when enabled, prevents a step change in phase on the input reference signals (pri or sec) from causing a step change in phase at the input of the dpll block of figure 1. during reference input rearrangement, such as during a s witch from the primary reference (pri) to the secondary reference (sec), a step change in phase on the input signa ls will occur. a phase step at the input of the dpll would lead to unacceptable phase changes in the output signal. 44 tdo test serial data out (cmos output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high im pedance state when jtag scan is not enable. 45 tdi test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . 46 trst test reset (input). asynchronously initialize s the jtag tap controller by putting it in the test-logic-reset state. if not used, this pin should be held low. 47 tck test clock (input): provides the clock to the jt ag test logic. this pin is internally pulled up to v dd . 48 tms test mode select (input). jtag signal that controls th e state transitions of the tap controller. this pin is internally pulled up to v dd . fs2 fs1 input frequency 0 0 19.44mhz 01 8khz 1 0 1.544mhz 1 1 2.048mhz pin description (continued) pin # name description
MT9045 data sheet 6 zarlink semiconductor inc. figure 3 - tie correction circuit as shown in figure 3, the tie corrector circuit receives one of the two reference (pri or sec) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the dpll. therefore, the virtual referenc e is a delayed version of the selected reference. during a switch from one reference to the other, t he state machine first changes the mode of the device from normal to holdover. in holdover mode, the dpll no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. the co mpare circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. this dela y value is passed to the programmable delay circuit (see figure 3). the new virtual reference signal is now at the same phase position as the previous reference signal would have been if the refe rence switch not taken place. the state machine then returns the device to normal mode. the dpll now uses the new virtual reference signal, and si nce no phase step took place at the input of the dpll, no phase step occurs at the output of the dpll. in other words, reference switching will not create a phase change at the input of the dpll, or at the output of the dpll. since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist bet ween the selected input reference signal and the output signal of the dpll. this phase error is a function of the difference in ph ase between the two input reference signals during reference rearrangements. each time a reference switch is made, the delay between input signal and output signal will change. the value of this delay is the accumulation of the error measured during each reference switch. the programmable delay circuit can be zeroed by applying a logic low pulse to the tie circuit reset (tclr ) pin. a minimum reset pulse width is 300ns. this results in a phase alignment between the input reference signal and the output signal as shown in figure 14. the speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel. the state diagram of figure 7 indicates which stat e changes the tie corrector circuit is activated. programmable delay circuit control signal delay value tclr resets delay compare circuit tie corrector enable from state machine control circuit feedback signal from frequency select mux pri or sec from reference select mux virtual reference to dpll
MT9045 data sheet 7 zarlink semiconductor inc. digital phase lock loop (dpll) as shown in figure 4, the dpll of the MT9045 consists of a phase detector, limiter, loop filter, digitally controlled oscillator, and a control circuit. figure 4 - dpll block diagram phase detector - the phase detector compares the virtual refere nce signal from the tie corrector circuit with the feedback signal from the frequency select mux circuit, and provides an error signal corresponding to the phase difference between the two. this error signal is passed to the limiter circuit. the frequency select mux allows the proper feedback signal to be externally selected (e.g., 8khz, 1.544mhz, 2.048mhz or 19.44mhz). limiter - the limiter receives the error signal from the phas e detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slo pe of 5ns per 125us. this is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms s pecified by at&t tr62411 and bellcore gr-1244-core, respectively. loop filter - the loop filter is similar to a first order low pa ss filter with a 1.9 hz cutoff frequency for all four reference frequency selections (8khz, 1. 544mhz, 2.048mhz or 19.44mhz). this f ilter ensures that the jitter transfer requirements in ets 300 011 and at&t tr62411 are met. control circuit - the control circuit uses status and control information from the state machine and the input impairment circuit to set the mode of the dpll. the three possible modes are normal, holdover and freerun. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchronization method of the dco is dependent on the state of the MT9045. in normal mode, the dco provides an output signal whic h is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequency equal to the last (less 30ms to 60ms) frequency the dco was generating while in normal mode. in freerun mode, the dco is free running with an a ccuracy equal to the accuracy of the osci 20mhz source. lock indicator - if the pll is in frequency lo ck (frequency lock means th e center frequency of the pll is identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then the lock signal will be set high. for specific lock indicator design recommendations see the applications - lock indicator section. control circuit state select from input impairment monitor state select from state machine feedback signal from frequency select mux dpll reference to output interface circuit virtual reference from tie corrector limiter loop filter digitally controlled oscillator phase detector
MT9045 data sheet 8 zarlink semiconductor inc. output interface circuit the output of the dco (dpll) is used by the output inte rface circuit to provide the output signals shown in figure 5. the output interface circuit uses four tapped delay line s followed by a t1 divider circuit, an e1 divider circuit, and a ds2 divider circuit to generate the required output signals. four tapped delay lines are used to generate 16. 384mhz, 12.352mhz, 12.624mhz and 19.44 mhz signals. the e1 divider circuit uses the 16.384mhz signal to generate four clock outputs and three frame pulse outputs. the c8o, c4o and c2o clocks are generated by simply dividing the c16o clock by two, four and eight respectively. these outputs have a nominal 50% duty cycle. the t1 divider circuit uses the 12.384mhz signal to generate the c1.5o clock by dividing the internal c12 clock by eight. this output ha s a nominal 50% duty cycle. the ds2 divider circuit uses the 12.624 mhz signal to gene rate the clock output c6o. this output has a nominal 50% duty cycle. figure 5 - output interface circuit block diagram the frame pulse outputs (f0o , f8o, f16o , tsp, and rsp) are generated directly from the c16 clock. the t1 and e1 signals are generated from a common dpll signal. consequently, all frame pulse and clock outputs are locked to one another for all operating states, and are also locked to the selected input reference in normal mode. see figures 14 & 16. all frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g., 30pf) loads. tapped delay line from dpll t1 divider e1 divider 16mhz 12mhz c1.5o c2o c4o c8o c16o f0o f8o f16o tapped delay line tapped delay line tapped delay line ds2 divider 12mhz 19mhz c6o c19o
MT9045 data sheet 9 zarlink semiconductor inc. input impairment monitor this circuit monitors the input signal to the dpll and automatically enables the holdover mode (auto-holdover) when the frequency of the incoming signal is outside the auto-holdover capture range. (see ac electrical characteristics - performance). this includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. when the incoming signal returns to norma l, the dpll is returned to normal mode with the output signal locked to the input signal. the holdover output signal in the MT9045 is based on the incoming signal 30ms minimum to 60ms prior to entering the holdover mode. the amount of phase drift while in holdover is negligible because the holdover mode is very accurate (e.g., 0.05ppm). consequently, the phase delay between the input and output after switching back to normal mode is preserved. state machine control as shown in figure 1, this state machine controls the reference select mux, the ti e corrector circuit and the dpll. control is based on the logic levels at the cont rol inputs rsel, ms1, ms2 and pcci (see figure 6). when switching from primary holdover to primary normal, th e tie corrector circuit is enabled when pcci = 1, and disabled when pcci = 0. all state machine changes occur synchronously on the risi ng edge of f8o. see the control and mode of operation section for full details. figure 6 - control state machine block diagram master clock the MT9045 can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section. control and mode of operation the active reference input (pri or sec) is selected by the rsel pin as shown in table 2. rsel input reference 0pri 1 sec table 2 - input reference selection ms1 ms2 to reference select mux to tie corrector enable control state machine to dpll state select pcci rsel
MT9045 data sheet 10 zarlink semiconductor inc. the MT9045 has three possible modes of operation, normal, holdover and freerun. as shown in table 3, mode/control select pins ms2 an d ms1 select the mode and method of control. refer to table 4 and figure 7 for details of the state change sequences. normal mode normal mode is typically used when a slave clock source, synchronized to the network is required. in normal mode, the MT9045 provides timing (c1.5o, c2o, c4o , c8o, c16o and c19o ) and frame synchronization (f0o , f8o, f16o , tsp and rsp) signals, which are synchronized to one of two reference inputs (pri or sec). the input reference signal may have a nominal freque ncy of 8khz, 1.544mhz, 2.048mhz or 19.44mhz. from a reset condition, the MT9045 will take up to 30 seco nds (see ac electrical characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. the selection of input references is control dependent as shown in state table 4. the reference frequencies are selected by the frequency control pins fs2 and fs1 as shown in table 1. fast lock mode fast lock mode is a submode of normal mode, it is used to allow the MT9045 to lock to a reference more quickly than normal mode will allow. typically, the pll will lock to the incoming reference within 500ms if the flock pin is set high. holdover mode holdover mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily disrupted. in holdover mode, the MT9045 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal. when in normal mode, and locked to the input reference signal, a numerical value corresponding to the MT9045 output reference frequency is stored alternately in two memory locations every 30ms. when the device is switched into holdover mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. this satisfies the at&t tr62411 and bellcore gr-1244-core stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). two factors affect the accuracy of holdover mode. one is dr ift on the master clock while in holdover mode, drift on the master clock directly affects the holdover mode accuracy. note that the ab solute master clock (osci) accuracy does not affect holdover accuracy, only the change in osci accuracy while in holdover. for example, a 32ppm master clock may have a temperature coefficient of 0.1ppm per degree c. so a 10 degree change in ms2 ms1 mode 0 0 normal 0 1 holdover 1 0 freerun 11 reserved table 3 - operating modes and states
MT9045 data sheet 11 zarlink semiconductor inc. temperature, while the MT9045 is in holdover mode may result in an additional offset (over the 0.05ppm) in frequency accuracy of 1ppm. which is much greater than the 0.05ppm of the MT9045. the other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. for instance, jitter of 7.5ui at 700hz may reduce the holdover mode accuracy from 0.05ppm to 0.10ppm. freerun mode freerun mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. in freerun mode, the MT9045 provides timing and synchroni zation signals which are based on the master clock frequency (osci) only, and are not synchronized to the reference signals (pri and sec). the accuracy of the output clock is equal to the accuracy of the master clock (osci). so if a 32ppm output clock is required, the master clock must also be 32ppm. see applications - crystal and clock oscillator sections. MT9045 measures of performance the following are some synchronizer performance indicators and their corresponding definitions. intrinsic jitter intrinsic jitter is the jitter produced by the synchronizing ci rcuit and is measured at it s output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. in the MT9045, the intrinsic jitter is limited to less than 0.02ui on the 2.048mhz and 1.544mhz clocks. jitter tolerance jitter tolerance is a measure of the ability of a pll to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnit udes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and freq uencies, and output jitter is measured with various filters depending on the applicable standards. for the MT9045, two internal elements determine the jitter attenuation. this includes the internal 1.9hz low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to 5ns/125us. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us.
MT9045 data sheet 12 zarlink semiconductor inc. the MT9045 has twelve outputs with three possible input frequencies (except for 19.44mhz, which is internally divided to 8khz) for a total of 36 possible jitter transf er functions. since all outpu ts are derived from the same signal, the jitter transfer values for the four cases, 8khz to 8khz, 1.544mhz to 1.544mhz and 2.048mhz to 2.048mhz can be applied to all outputs. it should be noted that 1ui at 1.544mhz is 644ns, wh ich is not equal to 1ui at 2.048mhz, which is 488ns. consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. what is the t1 and e1 output jitter wh en the t1 input jitter is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18db? using the above method, the jitter attenuation can be calcul ated for all combinations of inputs and outputs based on the three jitter transfer functions provided. note that the resulting jitter transfer functions for a ll combinations of inputs (8khz, 1.544mhz, 2.048mhz) and outputs (8khz, 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, 16.384mhz, 19.44mhz) for a given input signal (jitter frequency and jitter amplitude) are the same. since intrinsic jitter is always present, jitter attenuation wi ll appear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. for the MT9045, the freerun accuracy is equal to the master clock (osci) accuracy. holdover accuracy holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. for the MT9045, the storage value is determined while the device is in normal mode and locked to an external reference signal. the absolute master clock (osci) accuracy of the MT9045 does not affect holdover accuracy, but the change in osci accuracy while in holdover mode does. outputt1 inputt1 a ? 20 ------- ?? ?? 10 = outputt1 20 18 ? 20 -------- - ?? ?? 10 2.5ui t1 () == outpute1 outputt1 644ns () 488ns () ------------------- 3.3ui t1 () = = outpute1 outputt1 1uit1 () 1uie1 () --------------------- - =
MT9045 data sheet 13 zarlink semiconductor inc. capture range also referred to as pull-in range. this is the input frequ ency range over which the synchronizer must be able to pull into synchronization. the MT9045 capture range is equal to 230 ppm minus the accuracy of the master clock (osci). for example, a 32 ppm master clock results in a capture range of 198 ppm. the bellcore gr-1244-core standard, recommends that the pl l should be able to reject references that are off the nominal frequency by more than 17 ppm. the MT9045 provides two pins, prioor and secoor, to indicate whether the primary and secondary reference are within the 17 ppm of the nominal frequency. both references are monitored at the same time. prioor and secoor are updated every 1.0 to 1.5 second. the prioor and secoor pins on the MT9045 indicate whether the primary and secondary references are within +/- 17ppm of the pll center frequency. if the mast er oscillator clock input at the osci pin has an accuracy of +/-4.6ppm then the effective out of range limits of the prioor and secoor pins will be +/-21.6ppm. if there are no clock transitions at the primary and secondary reference inputs when the MT9045 is configured to operate with 8khz or 19.44mhz, t hen the prioor and secoor pins will provide a 50ns high pulse width occurring once every 1.26 seconds. the duration of the pulse width is dependent on the master clock frequency. if there are no clock transitions at the active reference pin, the MT9045 will automatically go to holdover mode and indicate this condition with the holdover pin. lock range this is the input frequency range over which the synchroni zer must be able to mainta in synchronization. the lock range is equal to the capture range for the MT9045. phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the out put signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. time interval error (tie) tie is the time delay between a given timing signal and an ideal timing signal. maximum time interval error (mtie) mtie is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. phase continuity phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the synchronizer af ter a signal disturbance due to a reference switch or a mode change. the observation period is usually the time fr om the disturbance, to just after the synchronizer has settled to a steady state. in the case of the MT9045, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference switches and all mode changes. th e total phase shift, depending on the switch or type of mode change, may accumulate up to 200 ns over many frames. the rate of change of the 200 ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. this meets the at&t tr62411 maximum phase slope requirement of 7.6ns/125us and bellcore gr-1244-core (81ns/1.326ms). mtie s () tiemax t () tiemin t () ? =
MT9045 data sheet 14 zarlink semiconductor inc. phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: ? initial input to output phase difference ? initial input to output frequency difference ? synchronizer loop filter ? synchronizer limiter although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. for instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope pe rformance (limiter) results in longer lock times. the MT9045 loop filter and limiter were optimized to meet the at&t tr62411 jitter transfer and phase slope requirements. consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. see ac electrical characteristics - performance for maximum phase lock time.
MT9045 data sheet 15 zarlink semiconductor inc. figure 7 - control state diagram description state input controls freerun normal (pri) normal (sec) holdover (pri) holdover (sec) ms2 ms1 rsel pcci s0 s1 s2 s1h s2h 0 0 0 0 s1 - s1 mtie s1 s1 mtie 0 0 0 1 s1 - s1 mtie s1 mtie s1 mtie 0 0 1 x s2 s2 mtie - s2 mtie s2 mtie 01 0 x / s1h / - / 01 1 x / s2h s2h / - 10 x x - s0 s0 s0 s0 legend: - no change / not valid mtie state change occurs with tie corrector circuit refer to control state diagram for state changes to and from auto-holdover state table 4 - control state table phase re-alignment phase continuity maintained (without tie corrector circuit) phase continuity maintained (with tie corrector circuit) notes: (xxx) ms2 ms1 rsel {a} invalid reference signal movement to normal state from any state requires a valid input signal {a} {a} s0 freerun (10x) s2h holdover secondary (011) s1h holdover primary (010) s2 normal secondary (001) s1 normal primary (000) (pcci=0) (pcci=1) s1a auto-holdover primary (000) s2a auto-holdover secondary (001)
MT9045 data sheet 16 zarlink semiconductor inc. MT9045 provides a fast lock pin (flock), which, when set high enables the pll to lock to an incoming reference within approximately 500 ms. MT9045 and network specifications the MT9045 fully meets all applicable pll requirements (intrinsic jitter/wander, jitter/wander tolerance, jitter/wander transfer, frequency accuracy, frequency hold over accuracy, capture range, phase change slope and mtie during reference rearrangement) for the following specifications. 1. bellcore gr-1244-core june 1995 for stratum 3, stratum 4 enhanced and stratum 4 2. at&t tr62411 (ds1) december 1990 for stratum 3, stratum 4 enhanced and stratum 4 3. ansi t1.101 (ds1) february 1994 for stratum 3, stratum 4 enhanced and stratum 4 4. etsi 300 011 (e1) april 1992 for single access and multi access 5. tbr 4 november 1995 6. tbr 12 december 1993 7. tbr 13 january 1996 8. tu-t i.431 march 1993 9. tu-t g.813 august 1996 for opti on1 clocks for 2048 kbit/s interfaces 10. itu-t g.812 june 1998 for type iv clocks for 1,544 kbit/s interf aces and 2,048 kbit/s interfaces applications this section contains MT9045 application specific details for clock and crystal operation, reset operation, power supply decoupling, and control operation. master clock the MT9045 can use either a clock or crystal as the master timing source. in freerun mode, the frequency tolerance at the clock outpu ts is identical to the frequency tolerance of the source at the osci pin. for applications not requiring an accu rate freerun mode, tolerance of the master timing source may be 100ppm. for applications requiring an accurate freerun mode, such as at&t tr62411, the tolerance of the master timing source must be no greater than 32ppm. another consideration in determining the accuracy of the master timing source is the desired capture range. the sum of the accuracy of the master timing source and the capture range of the MT9045 will always equal 230ppm. for example, if the master timing source is 100ppm, then the capture range will be 130ppm. clock oscillator - when selecting a clock oscillator, numerous parameters must be considered. this includes absolute freque ncy, frequency change over temperature, output ri se and fall times, outpu t levels and duty cycle.
MT9045 data sheet 17 zarlink semiconductor inc. figure 8 - clock oscillator circuit for applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. fox f7c-2e3-20.0mhz frequency: 20mhz tolerance: 25ppm 0c to 70c rise & fall time:10ns (0.33v 2.97v 15pf) duty cycle: 40% to 60% the output clock should be connected directly (not ac coupled) to the osci input of the MT9045, and the osco output should be left open as shown in figure 8. crystal oscillator - alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capaci tors is shown in figure 9. figure 9 - crystal oscillator circuit the accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. typically, for a 20mhz crystal specified with a 32pf load capacitance, each 1pf change in load capacitance contributes approximately 9ppm to the frequency devi ation. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor shown in figure 9 may be used to compensate for capacitive effe cts. if accuracy is not a concern, then the trimmer may be removed, the 39pf capacitor may be increased to 56pf, and a wider tolerance crystal may be substituted. +3.3v 20mhz out gnd 0.1uf +3.3v osco MT9045 osci no connection osco 56pf 1m ? 39pf 3-50pf 20mhz MT9045 osci 100 ? 1uh 1uh inductor: may improve stability and is optional
MT9045 data sheet 18 zarlink semiconductor inc. the crystal should be a fundamental mode type - not an overtone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to ge nerate spurious responses. the crystal specification is as follows. frequency: 20mhz tolerance: as required oscillation mode: fundamental resonance mode: parallel load capacitance: 32pf maximum series resistance:35 ? approximate drive level: 1mw e.g., r1b23b32-20.0mhz (20ppm absolute, 6ppm 0c to 50c, 32pf, 25 ? ) tie correction (using pcci) when primary holdover mode is entered for short time periods, tie correction should not be enabled. this will prevent unwanted accumulated phase change between the input and output. for instance, 10 normal to holdover to normal mode change sequences occur, and in each case holdover was entered for 2s. each mode change sequence could account for a phase change as large as 350ns. thus, the accumulated phase change could be as large as 3.5us, and, the overall mtie could be as large as 3.5us. ? 0.05ppm is the accuracy of holdover mode ? 50ns is the maximum phase continuity of the MT9045 from normal mode to holdover mode ? 200ns is the maximum phase continuity of the mt 9045 from holdover mode to normal mode (with or without tie corrector circuit) when 10 normal to holdover to normal mode change sequences occur without mtie enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns. however, there would be no accumulated phase change, since the input to output phase is re-aligned after every holdover to normal state change. the overall mtie would only be 350ns. reset circuit a simple power up reset circuit with about a 50us reset low time is shown in figure 10. resistor r p is for protection only and limits current into the rst pin during power down conditions. the reset low time is not critical but should be greater than 300ns. phase hold 0.05ppm 2s 100ns == phase state 50ns 200ns 250ns = + = phase 10 10 250ns 100ns + () 3.5us ==
MT9045 data sheet 19 zarlink semiconductor inc. figure 10 - power-up reset circuit lock indicator the lock pin toggles at a random rate when the pll is frequency locked to the input reference. in figure 11 the rc-time-constant circuit can be used to hold the high state of the lock pin. once the pll is frequency locked to the input reference, the minimum duration of lock pin?s high state would be 32ms and the maximum duration of lock pin?s low state would not exceed 1 second. the following equations can be used to calculate the charge and discharge times of the capacitor. t c = - r d c ln(1 ? v t+ /v dd ) = 240 s t c = capacitor?s charge time r d = dynamic resistance of the diode (100 ? ) c = capacitor value (1 f) v t+ = positive going threshold voltage of the schmitt trigger (3.0 v) v dd = 3.3 v t d = - r c ln(v t- /v dd ) = 1.65 seconds t d = capacitor?s discharge time r = resistor value (3.3 m ? ) c = capacitor value (1 f) v t- = negative going threshold voltage of the schmitt trigger (2.0 v) v dd = 3.3 v +3.3v rst r p 1k ? c 10nf r 10k ? MT9045
MT9045 data sheet 20 zarlink semiconductor inc. figure 11 - time-constant circuit a digital alternative to the rc-time-constant circuit is presented in figure 12. the circuit in figure 12 can be used to generate a steady lock signal. the circuit monitors the MT9045?s lock pin, as long as it detects a positive pulse every 1.024 seconds or less, the advanced lock output will remain high. if no positive pulse is detected on the lock output within 1.024 seconds, the advanced lock output will go low. figure 12 - digital lock pin circuit lock r=3.3m MT9045 in4148 lock 74hc14 74hc14 c=1 f +
MT9045 data sheet 21 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * supply voltage and operating temperature are as per recommended operating conditions. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any pin v pin -0.3 v dd + 0.3 v 3 current on any pin i pin 30 ma 4 storage temperature t st -55 125 c 5 48 ssop package power dissipation p pd 200 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units 1 supply voltage v dd 3.0 3.6 v 2 operating temperature t a -40 85 c dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units conditions/notes 1 supply current with: osci = 0v i dds 1.8 ma outputs unloaded 2 osci = clock i dd 50 ma outputs unloaded 3 cmos high-level input voltage v cih 0.7v dd v 4 cmos low-level input voltage v cil 0.3v dd v 5 input leakage current i il -15 15 av i =v dd or 0v 6 high-level output voltage v oh 2.4 v i oh = 10 ma 7 low-level output voltage v ol 0.4 v i ol = 10 ma
MT9045 data sheet 22 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. * supply voltage and operating temperature are as per recommended operating conditions. * timing for input and output signals is based on the worst case result of the cmos thresholds. * see figure 12. ac electrical characteristics - performance characteristics sym min max units conditions/ notes? 1 freerun mode accuracy with osci at: 0ppm -0 +0 ppm 5-9 2 32ppm -32 +32 ppm 5-9 3 100ppm -100 +100 ppm 5-9 4 holdover mode accuracy with osci at: 0ppm -0.05 +0.05 ppm 1,2,4,6-9,41 5 32ppm -0.05 +0.05 ppm 1,2,4,6-9,41 6 100ppm -0.05 +0.05 ppm 1,2,4,6-9,41 7 capture range with osci at: 0ppm -230 +230 ppm 1-3,6-9 8 32ppm -198 +198 ppm 1-3,6-9 9 100ppm -130 +130 ppm 1-3,6-9 10 phase lock time 30 s 1-3,6-15 11 output phase continuity with: reference switch 200 ns 1-3,6-15 12 mode switch to normal 200 ns 1-2,4-15 13 mode switch to freerun 200 ns 1-,4,6-15 14 mode switch to holdover 50 ns 1-3,6-15 15 mtie (maximum time interval error) 600 ns 1-15,28 16 output phase slope 45 us/s 1-15,28 17 reference input for auto-holdover with: 8khz, 19.44mhz -30k +30k ppm 1-3,6,9,10-12 18 1.544mhz -30k +30k ppm 1-3,7,10-12 19 2.048mhz -30k +30k ppm 1-3,8,10-12 ac electrical characteristics - timing parameter measurement voltage levels* - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym cmos units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v
MT9045 data sheet 23 zarlink semiconductor inc. figure 13 - timing parameter measurement voltage levels ac electrical characterist ics - input/output timing figure 14 - input to output timing (normal mode) t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf t rw t r15d t r2d t r8d v t v t v t v t pri/sec 8khz pri/sec 2.048mhz pri/sec 1.544mhz t rw t rw pri/sec 19.44mhz v t f8o t rw t r19d notes: 1. input to output delay values are valid after a tclr or rst with no further state changes
MT9045 data sheet 24 zarlink semiconductor inc. characteristics sym min max units 1 reference input pulse width high or low t rw 100 ns 2 reference input rise or fall time t irf 10 ns 3 8khz reference input to f8o delay t r8d -21 6 ns 4 1.544mhz reference input to f8o delay t r15d 337 363 ns 5 2.048mhz reference input to f8o delay t r2d 222 238 ns 6 19.44mhz reference input to f8o delay t r19d 46 57 ns 7f8o to f0o delay t f0d 111 130 ns 8f16o setup to c16o falling t f16s 25 40 ns 9f16o hold to c16o rising t f16h -10 10 ns 10 f8o to c1.5o delay t c15d -45 -25 ns 11 f8o to c6o delay t c6d -10 10 ns 12 f8o to c2o delay t c2d -11 5 ns 13 f8o to c4o delay t c4d -11 5 ns 14 f8o to c8o delay t c8d -11 5 ns 15 f8o to c16o delay t c16d -11 5 ns 16 f8o to tsp delay t tspd -6 10 ns 17 f8o to rsp delay t rspd -8 8 ns 18 f8o to c19o delay t c19d -15 5 ns 19 c1.5o pulse width high or low t c15w 309 339 ns 20 c6o pulse width high or low t c6w 70 86 ns 21 c2o pulse width high or low t c2w 230 258 ns 22 c4o pulse width high or low t c4w 111 133 ns 23 c8o pulse width high or low t c8w 52 70 ns 24 c16o pulse width high or low t c16wl 24 35 ns 25 tsp pulse width high t tspw 478 494 ns 26 rsp pulse width high t rspw 474 491 ns 27 c19o pulse width high t c19wh 25 35 ns 28 c19o pulse width low t c19wl 17 25 ns 29 f0o pulse width low t f0wl 234 254 ns 30 f8o pulse width high t f8wh 109 135 ns 31 f16o pulse width low t f16wl 47 75 ns 32 output clock and frame pulse rise or fall time t orf 9ns 33 input controls setup time t s 100 ns 34 input controls hold time t h 100 ns
MT9045 data sheet 25 zarlink semiconductor inc. figure 15 - output timing 1 figure 16 - output timing 2 t f16wl t f8wh t c15w t c15d t c4d t c16d t c8d t f16d t f0d f0o f16o c16o c8o c4o c2o c1.5o t c2d f8o t c4w t f0wl t c16wl t c8w t c2w t c8w t c4w v t v t v t v t v t v t v t v t t c19w c19o t c19d t c6d t c6w t c6w c6o t c19w v t v t t f16h t f16s t rspd t tspd tsp c2o t tspw t rspw v t v t v t v t rsp f8o
MT9045 data sheet 26 zarlink semiconductor inc. figure 17 - input controls setup and hold timing ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - intrinsic jitter unfiltered characteristics sym max u nits conditions/notes? 1 intrinsic jitter at f8o (8khz) 0.0002 uipp 1-15,22-25,29 2 intrinsic jitter at f0o (8khz) 0.0002 uipp 1-15,22-25,29 3 intrinsic jitter at f16o (8khz) 0.0002 uipp 1-15,22-25,29 4 intrinsic jitter at c1.5o (1 .544mhz) 0.030 uipp 1-15,22-25,30 5 intrinsic jitter at c2o (2 .048mhz) 0.040 uipp 1-15,22-25,31 6 intrinsic jitter at c6o (6 .312mhz) 0.120 uipp 1-15,22-25,32 7 intrinsic jitter at c4o (4.096mhz) 0.080 uipp 1-15,22-25,33 8 intrinsic jitter at c8o (8 .192mhz) 0.104 uipp 1-15,22-25,34 9 intrinsic jitter at c16o (16.384mhz) 0.104 uipp 1-15,22-25,35 10 intrinsic jitter at tsp (8khz) 0.0002 uipp 1-15,22-25,35 11 intrinsic jitter at rsp (8khz) 0.0002 uipp 1-15,22-25,35 12 intrinsic jitter at c19o (19.44mhz) 0.27 uipp 1-15,22-25,36 ac electrical characteristics - c1.5o (1.544mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes ? 1 intrinsic jitter (4hz to 100khz filter) 0.015 uipp 1-15,22-25,30 2 intrinsic jitter (10hz to 40khz filter) 0.010 uipp 1-15,22-25,30 3 intrinsic jitter (8khz to 40khz filter) 0.010 uipp 1-15,22-25,30 4 intrinsic jitter (10hz to 8khz filter) 0.005 uipp 1-15,22-25,30 t h t s f8o ms1,2, rsel, pcci v t v t
MT9045 data sheet 27 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - c2o (2.048mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes ? 1 intrinsic jitter (4hz to 100khz filter) 0.015 uipp 1-15,22-25,31 2 intrinsic jitter (10hz to 40khz filter) 0.010 uipp 1-15,22-25,31 3 intrinsic jitter (8khz to 40khz filter) 0.010 uipp 1-15,22-25,31 4 intrinsic jitter (10hz to 8khz filter) 0.005 uipp 1-15,22-25,31 ac electrical characteristics - 8khz input to 8khz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter attenuation for 1hz@0.01uipp input 0 6 db 1-3, 6, 10 -15, 22-23, 25, 29, 37 2 jitter attenuation for 1hz@0.54 uipp input 6 16 db 1-3,6,10 -15, 22-23, 25, 29, 37 3 jitter attenuation for 10hz@0.10uipp input 12 22 db 1-3, 6,10 -15, 22-23,25,29,37 4 jitter attenuation for 60hz@0.10uipp input 28 38 db 1-3,6,10-15, 22-23,25,29,37 5 jitter attenuation for 300hz@ 0.10uipp input 42 db 1-3,6,10 -15, 22-23,25,29,37 6 jitter attenuation for 3600hz@0.005uipp input 45 db 1-3,6,10 -15, 22-23,25,29,37
MT9045 data sheet 28 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 1.544mhz input to 1.544mhz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter attenuation for 1hz@20uipp input 0 6 db 1-3,7,10 -15, 22-23,25,30,37 2 jitter attenuation for 1hz@104uipp input 6 16 db 1-3,7,10 -15, 22-23,25,30,37 3 jitter attenuation for 10hz@20uipp input 12 22 db 1-3,7,10 -15, 22-23,25,30,37 4 jitter attenuation for 60hz@20uipp input 28 38 db 1-3,7,10 -15, 22-23,25,30,37 5 jitter attenuation for 300hz@20uipp input 42 db 1-3,7,10-15, 22-23,25,30,37 6 jitter attenuation for 10khz@0.3uipp input 45 db 1-3,7,10-15, 22-23,25,30,37 7 jitter attenuation for 100khz@0 .3uipp input 45 db 1-3,7,10-15, 22-23,25,30,37
MT9045 data sheet 29 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 2.048mhz input to 2.048mhz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter at output for 1hz@3.00uipp input with 40hz to 100khz filter 2.9 uipp 1-3,8,10 -15, 22-23,25,31,37 2 0.09 uipp 1-3,8,10 -15, 22-23,25,31,38 3 jitter at output for 3hz@2.33uipp input with 40hz to 100khz filter 1.3 uipp 1-3,8,10 -15, 22-23,25,31,37 4 0.10 uipp 1-3,8,10 -15, 22-23,25,31,38 5 jitter at output for 5hz@2.07uipp input with 40hz to 100khz filter 0.80 uipp 1-3,8,10-15, 22-23,25,31,37 6 0.10 uipp 1-3,8,10-15, 22-23,25,31,38 7 jitter at output for 10hz@1.76uipp input with 40hz to 100khz filter 0.40 uipp 1-3,8,10-15, 22-23,25,31,37 8 0.10 uipp 1-3,8,10-15, 22-23,25,31,38 9 jitter at output for 100hz@1.50uipp input with 40hz to 100khz filter 0.06 uipp 1-3,8,10-15, 22-23,25,31,37 10 0.05 uipp 1-3,8,10-15, 22-23,25,31,38 11 jitter at output for 2400hz@1.50uipp input with 40hz to 100khz filter 0.04 uipp 1-3,8,10-15, 22-23,25,31,37 12 0.03 uipp 1-3,8,10-15, 22-23,25,31,38 13 jitter at output for 100khz@0.20uipp input with 40hz to 100khz filter 0.04 uipp 1-3,8,10-15, 22-23,25,31,37 14 0.02 uipp 1-3,8,10-15, 22-23,25,31,36
MT9045 data sheet 30 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 8khz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 0.80 uipp 1-3,6,10 -15,22-23,25-27,29 2 jitter tolerance for 5hz input 0.70 uipp 1-3,6,10 -15,22-23,25-27,29 3 jitter tolerance for 20hz input 0.60 uipp 1-3,6,10 -15,22-23,25-27,29 4 jitter tolerance for 300hz input 0 .20 uipp 1-3,6,10 -15,22-23,25-27,29 5 jitter tolerance for 400hz input 0 .15 uipp 1-3,6,10 -15,22-23,25-27,29 6 jitter tolerance for 700hz input 0 .08 uipp 1-3,6,10 -15,22-23,25-27,29 7 jitter tolerance for 2400hz input 0.02 uipp 1-3,6,10 -15,22-23,25-27,29 8 jitter tolerance for 3600hz input 0.01 uipp 1-3,6,10 -15,22-23,25-27,29 ac electrical characteristics - 1.544mhz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 150 uipp 1-3,7,10 -15,22-23,25-27,30 2 jitter tolerance for 5hz input 140 uipp 1-3,7,10 -15,22-23,25-27,30 3 jitter tolerance for 20hz input 130 uipp 1-3,7,10 -15,22-23,25-27,30 4 jitter tolerance for 300hz input 3 5 uipp 1-3,7,10 -15,22-23,25-27,30 5 jitter tolerance for 400hz input 2 5 uipp 1-3,7,10 -15,22-23,25-27,30 6 jitter tolerance for 700hz input 1 5 uipp 1-3,7,10 -15,22-23,25-27,30 7 jitter tolerance for 2400hz input 4 uipp 1-3,7,10 -15,22-23,25-27,30 8 jitter tolerance for 10khz input 1 uipp 1-3,7,10 -15,22-23,25-27,30 9 jitter tolerance for 100khz input 0.5 uipp 1-3,7,10 -15,22-23,25-27,30
MT9045 data sheet 31 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? notes: voltages are with respect to ground (v ss ) unless otherwise stated. supply voltage and operating temperature are as per recommended operating conditions. timing parameters are as per ac electrical characteristics - timing parameter measurement voltage levels 1. pri reference input selected. 2. sec reference input selected. 3. normal mode selected. 4. holdover mode selected. 5. freerun mode selected. 6. 8khz frequency mode selected. 7. 1.544mhz frequency mode selected. 8. 2.048mhz frequency mode selected. 9. 19.44mhz frequency mode selected. 10. master clock input osci at 20mhz 0ppm. 11. master clock input osci at 20mhz 32ppm. 12. master clock input osci at 20mhz 100ppm. 13. selected reference input at 0ppm. 14. selected reference input at 32ppm. 15. selected reference input at 100ppm. 16. for freerun mode of 0ppm. 17. for freerun mode of 32ppm. 18. for freerun mode of 100ppm. 19. for capture range of 230ppm. 20. for capture range of 198ppm. 21. for capture range of 130ppm. 22. 25pf capacitive load. ac electrical characteristics - 2.048mhz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 150 uipp 1-3,8,10 -15,22-23,25-27,31 2 jitter tolerance for 5hz input 140 uipp 1-3,8,10 -15,22-23,25-27,31 3 jitter tolerance for 20hz input 130 uipp 1-3,8,10 -15,22-23,25-27,31 4 jitter tolerance for 300hz input 5 0 uipp 1-3,8,10 -15,22-23,25-27,31 5 jitter tolerance for 400hz input 4 0 uipp 1-3,8,10 -15,22-23,25-27,31 6 jitter tolerance for 700hz input 2 0 uipp 1-3,8,10 -15,22-23,25-27,31 7 jitter tolerance for 2400hz input 5 uipp 1-3,8,10 -15,22-23,25-27,31 8 jitter tolerance for 10khz input 1 uipp 1-3,8,10 -15,22-23,25-27,31 9 jitter tolerance for 100khz input 1 uipp 1-3,8,10 -15,22-23,25-27,31 ac electrical characteristics - osci 20mhz master clock input characteristics sym min max units conditions/notes ? 1 tolerance -0 +0 ppm 16,19 2 -32 +32 ppm 17,20 3 -100 +100 ppm 18,21 4 duty cycle 40 60 % 5 rise time 10 ns 6 fall time 10 ns
MT9045 data sheet 32 zarlink semiconductor inc. 23. osci master clock jitter is less than 2nspp, or 0.04uipp where1uipp=1/20mhz. 24. jitter on reference i nput is less than 7nspp. 25. applied jitter is sinusoidal. 26. minimum applied input jitter magnitude to regain synchronization. 27. loss of synchronization is obtained at slightly higher input jitter amplitudes. 28. within 10ms of the state, reference or input change. 29. 1uipp = 125us for 8khz signals. 30. 1uipp = 648ns for 1.544mhz signals. 31. 1uipp = 488ns for 2.048mhz signals. 32. 1uipp = 323ns for 3.088mhz signals. 33. 1uipp = 244ns for 4.096mhz signals. 34. 1uipp = 122ns for 8.192mhz signals. 35. 1uipp = 61ns for 16.384mhz signals. 36. 1uipp = 51.44ns for 19.44mhz signals. 37. no filter. 38. 40hz to 100khz bandpass filter. 39. with respect to reference input signal frequency. 40. after a rst or tclr . 41. master clock duty cycle 40% to 60%. 42. prior to holdover mode, device was in normal mode and phase locked.
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